VLSI
2019
1.Low-Power
Approximate Unsigned Multipliers With Configurable Error Recovery
2.A
High-Performance and Energy-Efficient FIR Adaptive Filter Using Approximate
Distributed Arithmetic Circuits
3Concurrent
Error Detectable Carry Select Adder with Easy Testability
4.Design
and Analysis of Approximate Redundant Binary Multipliers
5.Area–Delay–Energy
Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real
Data
6.A
Two-Speed, Radix-4, Serial–Parallel Multiplier
7.Formal
Probabilistic Analysis of Low Latency Approximate Adders
8.Low-Power
and Fast Full Adder by Exploring New XOR and XNOR Gates
9.RAP-CLA:
A Reconfigurable Approximate Carry Look-Ahead Adder
10.Design of Power and
Area Efficient Approximate Multipliers