1. Design of Power and Area Efficient Approximate Multipliers.
2.Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication.
3. A General Digit-Serial Architecture for Montgomery Modular Multiplication.
4. A Multilayer Approach to Designing Energy-Efficient and Reliable ReRAM Cross-Point Array System.
5. A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications.
6. Probability-Driven Multibit Flip-Flop Integration With Clock Gating.
7. Design and Implementation of Modified Signed-Digit Adder.
8. Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications.
9. Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes.
10. A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing.
11. Recursive Approach to the Design of a Parallel Self-Timed Adder.
12. Design and Analysis of Approximate Compressors for Multiplication.
13. Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating.
14. Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator.
15. Logical Effort for CMOS-Based Dual Mode Logic Gates.
16. Area–Delay–Power Efficient Carry-Select Adder.
17. A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing
18. Design and Implementation of Modified Signed-Digit Adder.
19. Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage.