IEEE 2015 VLSI
1. Recursive
Approach to the Design of a Parallel Self-Timed Adder.
2. Design
and Analysis of Approximate Compressors for Multiplication.
3. Design
Flow for Flip-Flop Grouping in Data-Driven Clock Gating.
4. Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator.
4. Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator.
5. Increase in Read Noise Margin of
Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage
6. Logical Effort for CMOS-Based Dual
Mode Logic Gates
7. Area-Delay
Efficient Binary Adders in QCA.
8. Design
and Implementation of Modified Signed-Digit Adder.
9. Area–Delay–Power Efficient
Carry-Select Adder
10. Low-Power Digital Signal Processor
Architecture for Wireless Sensor Nodes.
11. A High Speed Low Power CAM With a Parity
Bit and Power-Gated ML Sensing
12. Fault Tolerant Parallel
Filters Based on Error Correction Codes.
13. Low-Complexity Hardware
Design for Fast Solving LSPs with Coordinated Polynomial Solution.
14. Fully Reused VLSI
Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC
Applications.
15. Aging-Aware Reliable
Multiplier Design With Adaptive Hold Logic.
16. A 5.8-GHz Wideband TSPC
Divide-by-16/17 Dual Modulus Prescaler.
17. Software/Hardware Parallel
Long-Period Random Number Generation Framework Based on the WELL Method.
18. A Fully Digital Front-End
Architecture for ECG Acquisition System
With 0.5 V Supply.