1. Design of Power and Area Efficient Approximate Multipliers.
2. Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication.
3. A General Digit-Serial Architecture for Montgomery Modular Multiplication.
4. Active–Passive ΔΣ Modulator for High-Resolution and Low-Power Applications.
5.A Multilayer Approach to Designing Energy-Efficient and Reliable ReRAM Cross-Point Array System.
6. A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications.
7. Probability-Driven Multibit Flip-Flop Integration With Clock Gating.
8. Design and Implementation of Modified Signed-Digit Adder.
9.Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications.
10. Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes.
11. A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing.
12. Recursive Approach to the Design of a Parallel Self-Timed Adder.
13. Design and Analysis of Approximate Compressors for Multiplication.
14. Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating.
15. Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator.
16. Logical Effort for CMOS-Based Dual Mode Logic Gates.
17. Area–Delay–Power Efficient Carry-Select Adder.
18. A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing
19. Design and Implementation of Modified Signed-Digit Adder.
20. Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage.